One embodiment of the invention relates to a power transistor having a semiconductor volume in which a plurality of transistor cells connected in parallel, a laterally oriented, highly conductive semiconductor layer buried below the transistor cells in the semiconductor volume, and at least one connection, via which the buried semiconductor layer can be contact-connected from the top side of the power transistor, are provided. In one embodiment of the invention relates to a power transistor, having a semiconductor volume, in which a plurality of transistor cells connected in parallel and isolated from one another by trenches, a laterally oriented, highly conductive semiconductor layer buried below the transistor cells in the semiconductor volume, and at least one connection, via which the buried semiconductor layer can be contact-connected from the top side of the power transistor, are provided. In one embodiment of invention furthermore relates to a method for producing power transistors of this type.
FIG. 1 illustrates an example of a power transistor in which a laterally oriented, highly conductive semiconductor layer is buried below the transistor cells in the semiconductor volume.
A power transistor 1 has a semiconductor volume 2, in which a p−-doped layer 3, an n+-doped buried semiconductor layer (so-called buried layer) 4, an n−-doped epitaxial layer 5, an n+-doped source region 6, a p-doped body region 7, n+-doped wells 8 and p-doped wells 9 are provided. Gate electrodes 10 are furthermore provided, via which it is possible to generate current flows from the source region 6 into the epitaxial layer 5.
The n+-doped wells 8 serve for contact-connecting the n+-doped buried semiconductor layer 4, while the p-doped wells 9 serve for insulating the buried semiconductor layer 4 and the epitaxial layer 5 from adjacent transistor cells (only one transistor cell is illustrated in FIG. 1).
With respect to the construction illustrated in FIG. 1, the formation of the wells 8 and 9 requires a high temperature budget, since said wells have to reach very deep into the semiconductor volume 2. However, this entails a large lateral extent of the wells 8, 9, whereby the lateral extent of the power transistor 1 is high. The resistance that vertical current flows have to overcome within the buried semiconductor layer 4 constitutes a not inconsiderable proportion of the on resistance of the power transistor 1 and leads to an inhomogeneity of the potential distribution at avalanche, which is tantamount to a lower loading capacity of the power transistor. When a negative drain voltage is present, the buried semiconductor layer 4 injects a relatively large minority current into the substrate (p−-doped layer 3), which current has to be dissipated by means of complicated extraction ring constructions (not shown here) in order that the functioning of adjacent regions (analogue or logic circuit parts) is not disturbed.